Hangzhou Xuhong Technology Co.,Ltd
EN
中文
LVDS interface uses very low voltage swing (about 350mV) to transmit data on two PCBs or a pair of balanced cables through differential, that is, low voltage differential signal transmission. It is a digital video signal transmission mode developed to overcome the disadvantages of high power consumption and EMI when transmitting broadband high bit rate data by TTL level. The LVDS output interface is used in the industrial computer, which can make the signal transmit at the rate of several hundred Mbit / s on the differential PCB line or balanced cable. Because of the low voltage and low current drive mode, the low noise and low power consumption are realized.
|
eDP |
LVDS |
|
|
Data & clock line |
1-4 pairs of data lines
There is no separate clock line
|
More data lines
Separate clock line
|
|
Bit rate，perpair |
1.6,2.7,5.4Gbps |
945Mbps |
|
Total capacity |
1.6-21.6Gbps |
7.56Gbps |
|
Clock |
Embedded |
Each channel has a separate clock line |
|
Transmission type |
Packets of video, audio and other transmission data in extensible formats |
Last compressed video signal only |
|
Two way data channel |
1Mbps or720Mbps |
100kbps |
|
channel coding |
ANSI 8B/10B |
Serialized at 7x pixel clockrate |
|
Content protection |
HDCP |
None |
