An LVDS LCD is driven by sending correctly formatted image data and timing from a host/controller to the panel's receiving electronics. A serializer converts parallel video information into differential serial streams; the panel's timing and pixel-driving circuits use the received information to form the image.
The important quantities are not interchangeable: frame rate, pixel clock, LVDS link clock and serial bit rate describe different parts of the process. The example below explains why a two-pixel-per-clock implementation can use a 74.25 MHz link clock for a particular 1920 x 1080, 60 Hz timing. It is not a universal setting for every Full HD panel.
From the host controller to the LCD pixels
Typical functional path: host display engine → LVDS serializer → panel receiver/timing circuitry → panel drivers. These functions may be integrated rather than provided as separate chips. The interface transports video; it does not replace the panel power supply or backlight driver.
TI's HMI interface guide describes the conversion from a processor's parallel RGB output to serial LVDS inputs on an LCD module. Whether a separate serializer or bridge is needed depends on the host and panel interfaces. For basic terminology and color-depth definitions, start with our LVDS interface introduction.
Read the active area and blanking before calculating clock
Resolution describes the visible image area. A complete raster timing also contains blanking intervals between active lines and frames. TI's pixel-clock guide explains why blanking must be included. Use the panel's specified totals rather than adding an assumed percentage.
Htotal is the full line length, including active data and horizontal blanking. Vtotal is the number of lines in a complete frame, including vertical blanking. Check the units: Htotal may be written in individual pixel periods or in interface-clock cycles that carry more than one pixel.
For progressive timing, when Htotal is expressed in individual pixel periods: full-raster pixel-period rate = Htotal x Vtotal x frame rate. The line frequency is Vtotal x frame rate. Do not add blanking again after using totals that already include it.
DE (Data Enable) identifies valid active pixel data. HSYNC and VSYNC provide line and frame timing references where required. Some panels specify DE-based operation; others require synchronization signals. Infineon's display-timing guide illustrates why the timing mode must follow the panel documentation. DE-only does not mean that data, clock or blanking requirements disappear.
Worked example: why 148.5 MHz can become 74.25 MHz
Assume progressive 1920 x 1080 video, a 60 Hz frame rate and totals of 2200 pixel periods by 1125 lines. These are illustrative assumptions, not settings to copy into an unidentified display. The visible resolution alone does not determine the totals.
Timing calculation for this example only| Quantity | Calculation and meaning |
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| Active image and blanking | 1920 x 1080 visible pixels. The assumed totals add 280 pixel periods per line and 45 lines per frame for blanking. |
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| Frame period | 1 / 60 Hz = approximately 16.667 ms per complete frame, not an interlaced field. |
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| Line frequency and period | 1125 x 60 = 67,500 lines/s, or 67.5 kHz. Each line takes approximately 14.815 µs. |
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| Single-pixel-equivalent clock | 2200 x 1125 x 60 = 148.5 million pixel periods/s. At one pixel period per clock, this corresponds to 148.5 MHz. |
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| Two-pixel interface clock | If the compatible interface transfers two pixels per clock, 148.5 / 2 = 74.25 MHz. One link-clock period is approximately 13.468 ns. |
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| Horizontal counts in that clock's units | 2200 / 2 = 1100 total link-clock cycles per line; 1920 / 2 = 960 active cycles. Two pixels are handled together during each active cycle. |
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The same arithmetic appears in AMD's video-clocking example. That document concerns HDMI; only its general raster and pixels-per-clock calculation is relevant here, not its HDMI serial-link rules.
In a compatible dual-link LCD arrangement, the two links share the image data at the common link-clock rate. Their pixel assignment must match the panel. TI's DS90C387A is a concrete dual-pixel example with eight LVDS data streams and two identical output clocks. Its 48 RGB input bits represent two pixels with 24-bit color each, not 48-bit color per pixel.
Do not divide every clock value by two. A datasheet may already give the dual-pixel link clock, and a controller's clock labels can refer to different internal stages. Read the mode and units before comparing values. Different blanking, frame rates or link architectures can produce different clocks for the same visible resolution.
LVDS link clock is not the serial data rate
In the classic 7:1 display-link format, each data pair sends seven serial bits during one link-clock period. For example, TI's SN65LVDS93B serializes 28 input bits over four data pairs and sends a separate clock pair. Its forwarded clock remains at the input-clock frequency; the internal seven-times clock is used to serialize the data.
For a two-link implementation using this 7:1 format at 74.25 MHz, the calculation is 74.25 x 7 = 519.75 Mb/s per data pair. This is neither the complete interface's total rate nor the useful RGB image payload. The transferred words also contain control or unused bit positions, and blanking time is not visible image data.
Four data pairs do not include the clock pair. Likewise, eight data pairs in a dual-pixel example are not a complete connector pin list. Clock-pair routing, grounds, power and control connections depend on the actual design. The 7:1 relationship describes this classic display format, not every protocol that uses LVDS electrical signaling.
What must match before driving an LVDS panel?
Clock, timing mode and units
Check the specified clock range, active and total counts, frame rate, blanking, sampling edge and any required sync polarities. Respect relationships between parameters; do not combine unrelated minimum and maximum values into a new timing mode. A valid calculation does not establish that the panel or controller accepts it.
Pixel assignment and data mapping
Confirm the single/dual-link mode, bits per color, pixel assignment and exact VESA/JEIDA mapping. A matching clock does not correct a data-mapping mismatch. Use the module's mapping diagram; a selection-pin level from another model is not a universal rule.
Cable, power and system integration
Use the documented connector pinout, cable and power/backlight requirements for the complete model and revision. Do not trial-connect an unverified cable, reconnect internal panel cables while powered or use this timing example as a power-up sequence. Qualified integration work must follow the equipment documentation.
For a replacement project, continue with the industrial LVDS panel selection guide. If the source is eDP, see the separate eDP-to-LVDS conversion checklist; correct timing alone does not make different interfaces directly compatible.
Need help reviewing LVDS panel timing?
Send the complete panel model and suffix, host/controller model, timing table and data-mapping page if available. Include the required resolution and frame rate, application, quantity and delivery country. State whether you need a panel only or a review of controller and cable requirements. Compatibility must be checked against the exact product documents.
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